职位&公司对比

职位详情

• 南京
• 5-10年
• 本科

• 电路设计
• RTL设计
• Verilog

Responsibilities & Com来自BOSS直聘petencies： As a member of RF DFE FPGA R&D team, the candidate will be an important contributor of DFE FPGA RTL design, matlab algoritkanzhunhm modeling, verification or SoC application. Opportunity to deep dive in design of cutting edge RF SoC. Qualifications： 1. Education background: - Bachelor or above, major in Computer Science, Telecommunication Engineering or related. 2. Specific Skills, knowledge and competencies: - 5+ years FPGA/ASIC design, familiar with HDL design language and EDA tools. - Experience on RF algorithm (Such as DPD/CFR). - Experience on digital signal processing. - Experience on high speed interface (CPRI/eCPRI/JESD). - Better to have knowledge on baseband, LTE/NR RAN system architecture. 3. General competencies: - Strong communication skill. - Highly responsiblekanzhun, self-motivated and proactive working attitude. - Good team workBOSS直聘 spirit and willing to contribute to the team’s success. - Capable of managing changes and multi-tasks during the R&D phase. - Flue直聘nt in both oral and written English.